An integrated circuit is functionally tested to ascertain the performance of the circuit at specified conditions, and to isolate any faults in the circuit at the specified conditions. The specified conditions may include core clock pulse frequency, signal level voltage, and ambient temperature. A test system for the functional test generally includes the circuit-under-test coupled to a tester that is itself coupled to a computing device workstation.
In operation, the tester generates an at least one test-data sequence of pulses, and an at least one clock signal sequence of pulses, that are each sent to at least one port of the circuit-under-test die(s). Generally, the clock signal generated by the tester is at a lower frequency than the functional speed of the circuit-under-test, so the circuit-under-test die(s) includes a coupled frequency boosting circuit to receive the tester generated clock signal, raise the frequency of the pulses of the tester generated clock signal, and output a higher frequency clock signal to the circuit-under-test as the core clock.
In operation, the circuit-under-test generates at least one functional output pulse in response to receiving the test data input and the core clock, that is sent to at least one port of the circuit-under-test die and received by the tester. The circuit-under-test die(s) generally also includes an at least one scan latch test circuit coupled to the circuit-under-test to save at least one signal state of the circuit-under-test that is not normally observable in a functional output pulse. At a specified time, in response to a scan clock signal, the scan latches collectively generate a pulse train, each pulse of the pulse train representing a signal state saved in a scan latch, to an at least one port of the circuit-under-test die(s), and received by the tester.
Conventionally, the tester sends to the workstation the data received from the circuit-under-test. The workstation executes programs to analyze the data received from the tester, and to determine if the expected functional outputs from the circuit-under-test conform with expected values for each tester clock pulse of interest, and if the scan latch pulse train (or its signature) output conforms to the expected values, for each core clock pulse of interest.
Furthermore, conventionally the workstation defines and sends to the tester an identification of each clock at which to latch the scan latches, for each new test of the integrated circuit-under-test, in a header preceding the clock signal or the data input to the integrated circuit die. Each new test, even if the clock signal and the data remains the same, the header must be sent to the circuit-under-test only because a new scan latch clock must be transmitted to the circuit test die for initialization of built in test circuitry on the die(s).
What is needed is an apparatus and a method to compare the result of a test input with a passing or failing test exemplar result on the die and not to transmit for each iteration of the test the test data to the tester-workstation combination and analyze for each iteration of the test the data on the tester-workstation combination. What is needed is an apparatus and a method to change the scan latch timing of the clock signal automatically on the integrated circuit die(s) and not to generate the clock signal for each iteration of the test from the tester-workstation combination, and not to transmit for each iteration of the test the clock signal for each iteration.